The present disclosure relates generally to the field of semiconductor fabrication. In conventional practice, semiconductor fabrication begins with the provision of a semiconductor wafer, comprising silicon formed in a regular, crystalline structure. A circuit pattern is devised in which regions of the semiconductor wafer are intended to support NMOS and PMOS semiconductor components. These regions are isolated from each other with the formation of electronically inert isolation trenches. Each region is then doped with a type of dopant opposite the electronic nature of the components to be created thereupon. The formation of the electronic components then occurs upon this semiconductor wafer, and typically involves doping the electronically active areas of the semiconductor wafer with the desired type of dopant. For instance, NMOS components are formed by implanting a p-type dopant in a region of the semiconductor, and then forming the components by implanting an n-type dopant in order to create the electronically active regions of the NMOS component. A conductive gate may be formed spanning the electrically active areas, generally comprising a dielectric, such as a silicon oxide, over which is formed a gate electrode, such as a gate silicon layer (e.g., polycrystalline silicon) topped with a nickel silicide layer. An additional layer of dielectric may be formed over the component for electrical isolation from other components. The transistor gate may then be interconnected with other components during a metallization step, in which metal paths are formed to connect the electronically active areas of the components into a fully interconnected circuit.
The concepts described hereinabove are illustrated in FIG. 1, which presents a side view in section of a portion of a conventional semiconductor device. In this figure, the semiconductor device 10 comprises a silicon wafer 12, an area of which is designated to support either n-type or p-type electronic components. For an area intended to support NMOS components, the semiconductor substrate (an upper layer 14 of the silicon wafer 12) is doped with a p-type dopant, which will electronically insulate the NMOS components to be fabricated thereupon. Conversely, for an area intended to support PMOS components, the semiconductor substrate 14 is doped with an n-type dopant, which will electronically insulate the PMOS components to be fabricated thereupon. The area may also be electronically insulated from nearby structures by the formation of one or more isolation structures 16, such as a local oxidation of silicon (LOCOS) structure or an isolation trench. To form an electronic component like a transistor, a gate structure is formed, comprising, in one common design, a layer of dielectric material 18 over which is formed a gate silicon layer 20, such as polycrystalline silicon. Sidewall spacers 26 are formed adjacent to the gate silicon layer 20, where the region of the semiconductor substrate 14 under the sidewall spacers 26 will become a lightly doped source/drain extension region 24, which will contain a comparatively small amount of dopant. The regions 28 of the semiconductor substrate 14 adjacent to the gate structures 18, 20 and the sidewall spacers 26 are heavily doped with a dopant of the same type as the components to be formed. The regions 28 will function as the source and drain regions of the transistor. After the dopant implantations, the semiconductor 10 is exposed to a high temperature anneal, which “activates” the dopant ions implanted in the lightly-doped source/drain extension regions 24 and source/drain regions 28 by causing them to migrate into the crystalline structure of the silicon wafer 12, and also restores the regular lattice configuration of the silicon wafer 12 for consistent electronic flow.
Following the activation of the dopant, a nickel layer 22 is formed over the gate 18, 20 and at least one of the active areas 28. A second anneal is then performed that causes the nickel layer 22 to react with the silicon in the gate silicon layer 20 and in the semiconductor substrate 14 comprising the source and drain regions 28 to form a nickel silicide layer, which affords high conductance to the transistor gate 20 and the source and drain regions 28. Because nickel diffuses rapidly in silicon, the silicide forming anneal is often performed at a comparatively lower temperature than the dopant activating anneal in order to limit undesirable nickel diffusion from the nickel layer 22. The completion of these steps results in a functional NMOS or PMOS transistor.